VRM load line, droop and thermal analysis

We characterise a desktop VRM end to end: what the phase count actually buys, what the load line does to the rail during a current step, and how far the reported voltage sits from the real one. The bench closes with a measured load-line slope in milliohms, a scope capture of the release overshoot, a thermocouple-referenced offset for the board's VRM sensor, and a telemetry reference checked against clamp input power.

The bench§

Two boards, both open bench at 22 °C ambient, both with a 360 mm AIO so nothing incidental blows across the VRM heatsink. A tower cooler shifts VRM steady state enough to invalidate a comparison, and so does a case: record both beside every thermal figure.

• AM5: X670E, AGESA 1.2.0.3c, Ryzen 9 7950X, 2 × 16 GB DDR5 UDIMM. Vcore is VDDCR_CPU; VDDCR_SOC is a separate, much smaller bank.
• LGA1700: Z790, microcode 0x12B, Core i9-14900K. Vcore is board-supplied over SVID, with no on-package regulator in the path.

DMM

4½-digit, millivolt resolution on the 2 V range. Slope work only.

Oscilloscope

100 MHz or better, DC-coupled, 10:1 probe with the ground spring fitted. The 15 cm lead it ships with forms an inductive loop that manufactures its own overshoot.

Thermocouple

K-type, 0.2 mm bead on the PCB back behind the hottest power stage, logged at 1 Hz.

Clamp meter

DC, Hall effect, on the EPS 12 V conductors. The one independent measure of CPU input power.

IR thermometer

Settable emissivity, plus matte tape for every surface.

What the phase count actually is§

A Vcore VRM is N interleaved buck converters on one output node, each with its own PWM output, driver, high-side and low-side FET, inductor and share of the output capacitance.

Interleaving puts ripple at N times the switching frequency and gives the loop N correction opportunities per period. That, with lower per-stage current, is what phase count buys; anything in the marketing number that is not a controller loop buys none of it.

Doublers and teaming§

Consumer controllers carry six to eight loops across all outputs — XDPE132G5C, RAA229131, RAA229628, MP2857, MP2856. An "18 phase" board is not 18 loops, and the two mechanisms behind the number differ.

• Doubling. A doubler — IR3599, IR3598, ISL6617A — alternates one PWM between two power stages. Ripple frequency doubles and per-stage current halves, but the controller still runs N loops and senses per loop, so it cannot trim the stages independently. Doublers sit behind the bank on the board's back side, in pairs.
• Teaming. Two stages driven from one PWM simultaneously. Nothing interleaves, ripple frequency is unchanged: thermal spreading and current capacity, no transient improvement. Leaves no doubler ICs behind the socket.

Identifying what your board has§

1. Pull the heatsink, read the part number off the QFN nearest the bank, and take the loop count and output split from its datasheet.
2. Count inductors in the Vcore bank, one per power stage; count the SoC or VCCSA bank separately, the smaller group near the socket's top edge.
3. Look behind the bank: doubler ICs in pairs mean doubled, twice the loop count in inductors with nothing behind them means teamed.

Power stage ratings inflate the same way: a SiC654 or TDA21490 headline current is a package rating at a stated case temperature, not a board capability.

Load line, droop, and what LLC trades away§

Vcore falls as current rises, on purpose. Both vendors specify a load line — an effective source impedance in milliohms — because it centres the voltage window: steps undershoot on application and overshoot on release, and droop raises the idle point so both fit one envelope.

Load-line calibration compensates that droop: the controller raises the setpoint in proportion to sensed current, flattening the V/I line. Vendor numbering is not standardised or always monotonic, so measure the slope from two settled DC points thirty seconds apart, then repeat at a second level to learn which way your board counts.

R_LL [milliohm] = (V_idle - V_load) / (I_load - I_idle)

V   at the die-side capacitor bank, DMM
I   from telemetry already verified against the clamp

Overshoot on load release§

The failure mode that matters is not undershoot. When an all-core AVX load stops, package current can fall from over a hundred amps to single digits in under a microsecond; inductor current cannot follow, and the stored energy goes into the output capacitance faster than the loop can answer.

With droop intact the spike lands inside the window droop reserved. Flatten the line and the loaded voltage already sat near the setpoint, so the spike goes above it by roughly the droop you removed. That is why a high-LLC machine passes every stability test you own: nothing is failing, and what happens instead is wear. Electromigration, gate-oxide and bias-temperature stress scale superlinearly with peak voltage, and accumulate in events no telemetry samples and no counter records.

The SoC rail behaves the same way behind a much smaller bank, so if you are pushing memory too, characterise VDDCR_SOC droop before blaming timings — see DDR5 subtiming tuning.

Measuring Vcore instead of reading it§

Three software fields called some variant of "Vcore" disagree with each other and with the rail: they are different quantities.

SVI2/SVI3 or SVID VID

The voltage the CPU requested. Not a measurement of anything; it moves with the CPU's load-line model, not the board's behaviour.

VRM VOUT telemetry

The controller's ADC on its remote-sense pins — a real measurement at the sense tap, but filtered, quantised to millivolts, and read over a slow bus. Kilohertz sampling against a microsecond event averages.

Super I/O core voltage

A divided analog rail into an on-chip ADC with a vendor-chosen divider and calibration. Useful for confirming a rail exists.

To get the rail, probe it. Where a board carries labelled measurement pads — ASUS brands the header ProbeIt — use them with the ground pad in the same block. Otherwise land on the output capacitor bank between the inductors and the socket, grounding to a pad in that bank: a ground that leaves the VRM area puts every switching current in the loop between your probe tips.

Position matters more than instrument grade. The capacitor bank sits before the socket contact resistance and the package delivery network, both part of the specified load line, so a reading there is optimistic under load. The die-side array under the socket is the closest accessible node.

The DMM is wrong for anything but slope: hundreds of milliseconds of aperture, ripple averaged out, a 20 µs event invisible. For transients use DC coupling, the 20 MHz bandwidth limit on, the ground spring, tens of millivolts per division with the offset pushed up, and a trigger on the falling load edge — capture the release, not the application.

Current and power telemetry§

Every power limit the CPU enforces — PPT, TDC and EDC on AM5, PL1, PL2 and ICCmax on LGA1700 — is computed from a current the CPU did not measure. The controller senses inductor current across the DCR, and firmware scales it into amps with a board constant; get that constant wrong and every downstream number is wrong the same way.

• On AM5 it is a current telemetry reference, one for VDDCR_CPU and one for VDDCR_SOC. Under-report and the CPU believes it is under PPT when it is not: boost holds longer, power and VRM temperature climb. Over-report and the same chip throttles early.
• On LGA1700 the pair is IA AC Load Line and IA DC Load Line, on most boards in hundredths of a milliohm. AC_LL sets the droop the CPU asks for; DC_LL is what it uses to reconstruct its own voltage and power. Mismatch DC_LL and reported package power is wrong, along with every limit built on it.

DCR sensing drifts: copper resistance rises about 0.39 % per °C, so the sense element tracks bank temperature and the controller's NTC compensation is only as good as the board's tuning. Expect reported current to differ hot and cold at identical load.

The one independent check is at the input: clamp the EPS 12 V conductors, measure the rail at a connector pin, take the product at a settled load. VRM efficiency at load is a wide band, so this catches gross error only; a twenty or thirty percent gap against reported package power is a telemetry reference problem, not noise.

This reaches past power accounting: boost residency runs on the same reported current, so a wrong reference shifts the frequency the chip picks at a given workload. Verify telemetry before touching offsets; see per-core curve optimizer.

VRM thermals§

The board's VRM sensor is usually an NTC on the PCB beside the bank: it reads board copper, lags the FET junction by tens of seconds, and reads low by an offset nobody publishes. Some report the stages' own TMON output instead, far closer to the junction, and the sensor name does not say which you have.

The stack from junction to air is junction, case, pad, heatsink, air, and every interface drops. The pad is the worst: badly seated or over-thick, it puts the difference into the junction while the heatsink surface reads comfortable. Characterise the offset once, then treat the onboard sensor as relative only.

1. Tape the thermocouple to the back of the PCB opposite the hottest stage; back-side copper couples well to its pad and the placement is repeatable.
2. Run a sustained all-core load to a plateau; twenty minutes at least, since the first ten are still rising.
3. Record thermocouple, onboard sensor and an IR read of the inductor tops at one instant; that difference is your offset, valid for that cooler, enclosure and ambient only.

Airflow is a configuration variable, not an ambient condition. Open bench with an AIO gives no flow over the VRM, a tower cooler some, and a case with a top-mounted radiator can be worse than the bench with the bank in exhaust. A 40 mm fan on the sink shifts the plateau and invalidates every later comparison, so record it or remove it.

At the controller's thermal limit the behaviour is not gradual: it asserts VR_HOT, or the AM5 equivalent, and the CPU drops to a low P-state at once. The signature is a clock cliff at normal package temperature: if core temperature looks fine and clocks collapsed, stop looking at the cooler.

Instrumenting from Linux§

Start with what the kernel has.

/sys/class/hwmon/hwmon*/name

for h in /sys/class/hwmon/hwmon*; do
  printf '%s\t%s\n' "${h##*/}" "$(cat "$h"/name)"
done

hwmon0	nvme
hwmon1	k10temp
hwmon2	nct6799
hwmon3	amdgpu

Then read the hwmon node directly; sensors only formats the same files, and sensors -u prints them raw.

/sys/class/hwmon/hwmon2/

grep -H . /sys/class/hwmon/hwmon2/temp*_label
grep -H . /sys/class/hwmon/hwmon2/temp*_input    # millidegrees C
grep -H . /sys/class/hwmon/hwmon2/in*_input      # millivolts

What you get is bounded by what the vendor wired up, whether the driver knows the board, and whether ACPI releases the chip.

nct6775

Split into nct6775_core and nct6775_platform. On many boards it will not bind: firmware claims the Super I/O region and the probe fails on an ACPI resource conflict. acpi_enforce_resources=lax forces it, at the cost of kernel and EC both driving one chip — a diagnostic, not a configuration.

asus_ec_sensors

Mainline, and the correct source for VRM temperature on supported ASUS boards, where that sensor hangs off the EC rather than the Super I/O. It carries a board allowlist; an unlisted board gets nothing.

k10temp

Tctl and per-CCD die temperature on AM5. The SVI voltage and current fields earlier Zen generations exposed are gone: in0_input and curr1_input do not exist on a 7000-series part.

For package power use the RAPL counter, not a sensor: a firmware model rather than a measurement, but the model the CPU enforces limits with.

perf stat -a -e power/energy-pkg/ -- sleep 60
cat /sys/class/powercap/intel-rapl:0/energy_uj   # microjoules, wraps
turbostat --quiet --show Core,Bzy_MHz,PkgWatt,PkgTmp --interval 1

Two out-of-tree options extend this, both needing care. zenpower3 decodes the SVI rails on some Zen 3 and Zen 4 parts, conflicts with k10temp, and carries per-SKU scaling constants. ryzen_smu exposes the SMU table at /sys/kernel/ryzen_smu_drv/pm_table; its layout changes with AGESA, and a mismatched version parses to plausible nonsense rather than an error, so check pm_table_version first.

The ceiling is firm: the controller's own PMBus telemetry goes to the EC, not a header, so nothing in hwmon reaches it. Past this point you are on the probes.

Failure table§

Validation§

Three load shapes, because they fail in different places.

# sustained: thermal plateau, VRM limit, steady-state droop
stress-ng --cpu 0 --cpu-method all --timeout 60m --metrics-brief

# transient: one second on, one second off, thirty minutes of edges
for i in $(seq 1 900); do
  stress-ng --cpu 0 --cpu-method fft --timeout 1 --quiet
  sleep 1
done

# after each run
journalctl -k --since "2 hours ago" | grep -iE 'mce|hardware error'
ras-mc-ctl --errors

On the sustained run watch the VRM plateau and the clock floor together: a clock cliff at normal core temperature is the VRM, and it will not show in the first ten minutes. On the transient run watch for machine checks, where undershoot failures land. The release capture is a scope job: trigger on the falling current edge, take twenty releases from the heaviest load the part accepts, and record the worst peak.

Anything that changes current at a given frequency invalidates all three: a per-core undervolt moves the operating point along the load line and changes droop and release energy together, so re-measure after curve work — see per-core curve optimizer.