Tuning is a measurement problem
before it is a settings problem.
Five long notes on the parts of a desktop platform that reward instrumentation: DDR5 subtimings and the refresh window, what a regulator really delivers under a transient, the shape of a per-core voltage curve, the SPI flash the board boots from, and where the PCIe lanes actually go.
Nothing here is a settings list. Every note gives the method, the instrument, and the validation run — because the number that worked on this bench is not the number that will work on yours.
Memory & Fabric
Subtiming work on DDR5, and the lane topology the rest of the platform hangs off.
2 notes
Power & Thermals
What the regulator actually delivers under load, and how the voltage/frequency curve is shaped.
2 notes
All notes
| Note | Section | Read | Risk | Revised |
|---|---|---|---|---|
| DDR5 subtiming tuning on AM5 and LGA1700 Hand-tuning DDR5 subtimings, with the refresh window as the largest single lever | Memory & Fabric | 16 min | risk: moderate | 2026-08-28 |
| PCIe lane topology, bifurcation and link verification Splitting a x16 root port and proving on Linux that every link trained as intended | Memory & Fabric | 16 min | risk: low | 2026-08-28 |
| VRM load line, droop and thermal analysis What the phase count buys, what LLC costs, and how to measure a rail software cannot see | Power & Thermals | 16 min | risk: moderate | 2026-08-28 |
| Per-core Curve Optimizer: finding each core's voltage floor Per-core CO counts found by bisection, validated at idle rather than under load | Power & Thermals | 16 min | risk: moderate | 2026-08-28 |
| UEFI firmware inspection, modification and recovery Read the SPI chip, write one region back, and recover a board that will not POST | Firmware | 16 min | risk: can brick | 2026-08-28 |